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1 ? fn6412.1 isl6423b single output lnb supply and control voltage regulator with i 2 c interface for advanced satellite set-top box designs the isl6423b is a highly integrated voltage regulator and interface ic, specifically designed for supplying power and control signals from advanced satellite set-top box (stb) modules to the low noise blocks (lnbs) of singe antenna ports. the device consists of a current-mode boost pwm and a low-noise linear regulator along with the circuitry required for 22khz tone generation, modulation and i 2 c device interface. the device makes the total lnb supply design simple, efficient and compact with low external component count. the current-mode boost converters provides the linear regulator with input voltage that is set to the final output voltages, plus typically 0.8v to insure minimum power dissipation across each linear regulator. this maintains constant voltage drop across the linear pass element while permitting adequate voltage range for tone injection. the final regulated output voltage is available at output terminals to support the operation of an antenna port for single tuners. the outputs for each pwm can be controlled in two ways, full control from i 2 c using the vtop and vbot bits or set the i 2 c to the lower range i.e., 13v/14v, and switch to higher range i.e., 18v/19v, with the selvtop pin. all the functions on this ic are controlled via the i 2 c bus by writing 8 bits words onto the system registers (sr). the same register can be read back, and five i 2 c bits will report the diagnostic status. separate enable command sent on the i 2 c bus provides for standby mode control for the pwm and linear combination, disabling the output and forcing a shutdown mode. the output channel is capable of providing 750ma of continuous current. the overcurrent limit can be digitally programmed to four levels. the external modulation input extm can accept a modulated diseqc command and tr ansfer it symmetrically to the output. alternatively the extm pin can be used to modulate the continuos internal tone. the flt pin serves as an interrupt for the processor when any condition turns off t he lnb controller (over temperature, overcurrent, disabled). the nature of the disable can be read of the i 2 c registers. features ? single chip power solution - operation for 1-tuner/1-dish applications - integrated dc/dc converter and i 2 c interface ? switch-mode power converter for lowest dissipation - boost pwms with >92% efficiency - selectable 13.3v or 18.3v outputs - digital cable length compensation (1v) -i 2 c and pin controllable output ? output back bias capability of 28v ?i 2 c compatible interface fo r remote device control ? registered slave address 0001 00xx ? 2.5v, 3.3v, 5v logic compatible ? external pin to toggle between v and h polarization ? built-in tone oscillator factory trimmed to 22khz - facilitates diseqc (eutelsat) encoding - external modulation input ? internal over-temperature protection and diagnostics ? internal ov, uv, overload and overtemp flags (visible on i 2 c) ?flt signal ? lnb short-circuit protection and diagnostics ? qfn, eptssop packages ? pb-free available (rohs compliant) applications ? lnb power supply and control for satellite set-top box ordering information part number* part marking temp. (c) package pkg. dwg. # isl6423berz (note) 6423berz -20 to +85 24 ld 4x4 qfn (pb-free) l24.4x4d isl6423bevez (note) isl6423bevez -20 to +85 28 ld eptssop (pb-free) m28.173b note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. add ?-t? suffix for tape and reel. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. april 10, 2007
2 fn6412.1 april 10, 2007 pinouts isl6423b (28 ld eptssop) top view isl6423b (24 ld qfn) top view vcc nc flt sgnd sgnd tcap addr0 addr1 bypass pgnd gate vsw nc cs cpswin cpvout extm sda scl tdin nc nc agnd selvtop txt cpswout tdout vo 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sgnd flt vcc cpswin cpswout cpvout gate vsw cs txt selvtop agnd sgnd tcap addr0 addr1 bypass pgnd extm sda scl tdout tdin vo 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112
3 fn6412.1 april 10, 2007 block diagram note: 1. pinouts shown are for the qfn package. counter overcurrent protection logic scheme 1 olf/bcf dcl oc1 clk1 pwm logic q s gate pgnd cs cs amp ilim1 slope compensation
4 fn6412.1 april 10, 2007 typical application schematic qfn r13 4.7k r22 47k r23 10k m6 nds356ap l4 220h 1 2 c15 0.22f r7 15 extm c16 10n flt bar tdout q2 tpc6002 1 2 3 4 5 6 d5 cms06 d6 cms06 rtn r8 0.1 r9 470 r10 18 0 d7 cms06 c18 10f c19 10f c20 10f 0 sda 0 0 scl 0 selvtop l5 15h 1 2 c21 100pf 0 0 txt 0 c22 56f c23 56f 0 c24 1f 0 l6 4.7h 1 2 c25 47n c26 1f vlnb r11 100 r12 100 c27 0.22f c28 0.1f vin rtn 0 d8 1.5ke24 u2 isl6423er vsw 8 cs 9 selvtop 11 txt 10 agnd 12 cpvout 19 extm 18 scl 16 tdin 14 tdout 15 addr0 3 vo 13 cpswout 20 addr1 4 bypass 5 vcc 22 cpswin 21 sgnd 1 tcap 2 flt 23 pgnd 6 24 sda 17 gate 7 0 c29 1n r24 4.7k note : sda and scl require pull up to the required logic level. q4 2n2222a sgnd
5 fn6412.1 april 10, 2007 absolute maximum rati ngs thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v to 18.0v logic input voltage range (sda, scl, ent, dsqin 1 and 2, sel18v 1 and 2) . -0.5v to 7v thermal resistance (typical, notes 2, 3) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 2.
6 fn6412.1 april 10, 2007 tone oscillator tone frequency f tone ent = h 20.0 22.0 24.0 khz tone amplitude v tone ent = h, i o = 5ma 500 680 800 mv tone duty cycle dc tone ent = h, 40 50 60 % tone rise or fall time t r , t f ent = h, 5 10 14
7 fn6412.1 april 10, 2007 oscillator oscillator frequency f o fixed at (20)(f tone ) 396 440 484 khz thermal shutdown temperature shutdown threshold - 150 - c temperature shutdown hysteresis - 20 - c otfi flt (released) v o = 6v - - 10
8 fn6412.1 april 10, 2007 typical performance curves figure 2. output current derating (eptssop) f igure 3. output current derating (4x4 qfn) 020406080 temperature (c) i out (a) i out _max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 020406080 temperature (c) i out (a) i out _max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 functional pin description symbol function sda bidirectional data from/to i 2 c bus. scl clock from i 2 c bus. vsw input of the linear post-regulator. pgnd dedicated ground for the output gate driver of respective pwm. cs current sense input; connect the sense re sistor rsc at this pin for desired peak overcurrent value for the boost fet. the set peak limit is effective in the static mode current limit only i.e., dcl = high. sgnd small signal ground for the ic. tcap capacitor for setting rise and fall time of the output voltage. typical value is 0.1f. bypass bypass capacitor for internal 5v. txt txt is the tone transmit signal input used to change t he tone decoder threshold from txt = 0, 200mv max during receive to txt = 1, 400mv min during transmit. vcc main power supply to the chip. gate this output drives the boost fet gate. the output is held low when v cc is below the uvlo threshold. vo output voltage for the lnb is available at vo pin. addr0 & addr1 logic combination at the addr0 & 1 can select four different chip select addresses. extm this pin can be used in two ways: 1) as an input for externally modul ated diseqc tone signal which is tr ansferred to the symmetrically onto v out 2) alternatively apply a diseqc modulati on envelope which modulates an internal tone and then transfers it symmetrically onto v out flt this is an open drain output from the controller. when the flt goes low it indicates that an over temperature, over load fault, uvlo, or an i 2 c reset condition has occurred. the pr ocessor should then look at the i 2 c register to get the actual cause of the error. a high on the flt indicates that the device is functioning normally. cpvout, cpswin cpswout a 47n charge pump decoupling capacitor is to be connected to cpvout. connect a 1.5n capacitor between cpswin and cpswout selvtop when this pin is low the v out is in the 13v, 14v range selected by the i 2 c bit vbot. when this pin is high the 18v, 19v range selected by the i 2 c bit vtop. the voltage select pin enable vspen i 2 c bit must be set low for the selvtop pins to be active. setting vspen hi gh disables this pins and voltage selection will be done using the i 2 c bits vbot and vtop only. tdin, tdout tdin is the tone decoder input and tdout is the tone detector output. tdout is an open drain output
9 fn6412.1 april 10, 2007 functional description the isl6423b single output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. the device utilizes built-in dc/dc step up converters that, operates from a single supply source ranging from 8v to 14v, and generates the voltage needed to enable the linear post-regulator to work with a minimum of dissipated power. an undervoltage lockout circuit disables the device when vcc drops below a fixed threshold (7.5v typ). diseqc encoding the internal oscillator is factor y-trimmed to provide a tone of 22khz in accordance with diseqc (eutelsat) standards. no further adjustment is require d. the tone oscillator can be controlled either by the i 2 c interface (ent bit) or by a dedicated pin (extm) that allows immediate diseqc data encoding separately for each lnb. all the functions of this ic are controlled via the i 2 c bus by writing to the system registers. the same registers can be read back, and four bits will report the diagnostic status . the internal oscillator operates the converters at twenty times the 22k tone frequency. the device offers full i 2 c compatibility, and supports 2.5v, 3.3v or 5v logic, up to an operational speed of 400khz. if the tone enable (ent) bit is set low and the msel bits set low through i 2 c, then the extm terminal activates the internal tone signal, modulating the dc output with a 680mv pp typical symmetrical tone waveform. the presence of this signal usually provides the lnb with information about the band to be received. burst coding of the tone can be accomplished due to the fast response of the extm input and rapid tone response. this allows implementation of the diseqc (eutelsat) protocols. when the ent bit is set high, a continuous 22khz tone is generated regardless of the extm pin logic status for the regulator channel lnb-a. the ent bit must be set low when the extm pin is used for diseqc encoding. the extm accepts an externally modulated tone command when the msel i 2 c bit is set high and ent is set low. diseqc decoder tdin is the input to the tone decoder. it accepts and the tone signal derived from the v out thru the 10nf decoupling capacitor. the detector threshold can be set to 200mv max in the receive mode and to 400mv min in the transmit mode by means of the logic pres ented to the txt pin. if tone is detected the open drain pin tdout is asserted low. this enables the tone diagnostics to be performed, apart from the normal tone detection function. linear regulator the output linear regulator will sink and source current. this feature allows full modulation capability into capacitive loads as high as 0.75 ------------------ - = (eq. 1)
10 fn6412.1 april 10, 2007 however, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is selected. this can be solved by initiating any power start-up in static mode (dcl = high) and then switching to the dynamic mode (dcl = low) after a predetermined interval. when in static mode, the olf bit goes high when the current clamp limit is reached and returns low at the end of initial power-on soft-start. in the static mode the output current thr ough the linears is limited to a 990ma typ. when a 19.3v line is connected onto a vout1 or 2 that has been set to 13.3v the linear will then enter a back current limited state. when a back cu rrent of greater than 140ma typical is sensed at the lower fet of the linear for a period greater that 2ms the output is disabled for a period of 50ms and the bcf bit is set. if the 19.3v remains connected, the output will cycle thro ugh the on = 2ms/off = 50ms. the output will return to the setpoint when the fault is removed. bcf bit is set high during the 50ms off period. thermal protection this ic is protected against overheating. when the junction temperature exceeds +150c (typ ical), the step-up converter and the linear regulator are shut off and the otf bit of the sr is set high. when the junction is cooled down to +130c (typical), normal operation is resumed and the otf bit is reset low. if a part is repe atedly driven to the overtemp shutdown temperature the chip is latched off after the fourth occurrence and the i 2 c otf bit is latched high and flt_bar low. this otf counter and flt_bar can be reset and the chip restarted by either a power down/up and reload the i 2 c or power can be left on and the reset accomplished by toggling the i 2 c bit en low then back high. external output voltage selection when the i 2 c bit vspen is set high the output voltage can be selected by the i 2 c bus. additionally, the package offers the pin selvtop for independent 13 thru 19v output voltage selection., when the vspen bit is set low. a summary of the voltage control is given in table 1. for further details refer to the individual registers sr1 and sr3 i 2 c bus interface for isl6423b (refer to philips i 2 c specification, rev. 2.1) data transmission from main microprocessor to the isl6423b and vice versa takes place through the two wire i 2 c bus interface, consisting of the two lines sda and scl. both sda and scl are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (pull up resistors to positive supply voltage must be externally connected). when the bus is free, both lines are high. the output stages of isl6423b will have an open drain/open collector in order to perform the wired-and function. data on the i 2 c bus can be transferred up to 100kbps in the standard-mode or up to 400kbps in the fast-mode. the level of logic ?0? and logic ?1? is dependent of associated value of v dd as per electrical specification table. one clock pulse is generated for each data bit transferred. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 4. start and stop conditions as shown in figure 5, start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. table 1. vspen vtop vbot selvtop vout 0 x 0 0 13.3v 0 x 1 0 14.3v 0 0 x 1 18.3v 0 1 x 1 19.3v 1 0 0 x 13.3v 1 0 1 x 14.3v 1 1 0 x 18.3v 1 1 1 x 19.3v sda scl data line stable data valid change of data allowed figure 4. data validity sda scl start condition figure 5. start and stop waveforms stop condition sp
11 fn6412.1 april 10, 2007 byte format every byte put on the sda line must be eight bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transfe rred with the most significant bit first (msb). acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (figure 6). the peripheral that acknowledges has to pull down (low) the sda line during the acknowled ge clock pulse, so that the sda line is stable low during this clock pulse. (of course, set-up and hold times must also be taken into account.) the peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case , the master transmitter can generate the stop information in order to abort the transfer. the isl6423b will not generate the acknowledge if the power ok signal from the uvlo is low. transmission without acknowledge avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. this approach, though, is less protected from error and decreases the noise immunity. isl6423b software description interface protocol the interface protocol is co mprised of the following, as shown below in table 2: ? a start condition (s) ? a chip address byte (msb on left; the lsb bit determines read (1) or write (0) transmission) (the assigned i 2 c slave address for the isl6423b is 0001 0 xx x) ? a sequence of data (1 byte + acknowledge) ? a stop condition (p) system register format ? r, w = read and write bit ? r = read-only bit all bits reset to 0 at power-on table 6. control register (sr4) transmitted data ( i 2 c bus write mode) when the r/w bit in the chip is set to 0, the main microprocessor can write on th e system registers (sr2 thru sr4) of the isl6423b via i 2 c bus. these will be written by the microprocessor as shown below. the spare bits of registers can be used for other functions. sda scl figure 6. acknowledge on the i 2 c bus 1 2 8 9 acknowledge from slave msb start table 2. interface protocol s00010a1a0r/wackdata (8 bits)ackp table 3. status register (sr1) r, wr, wr, wrrrrr sr1h sr1m sr1l otf cabf ouvf olf bcf table 4. tone register (sr2) r, w r, w r, w r, w r, w r, w r, w r, w sr2h sr2m sr2l ent msel tth x x table 5. command register (sr3) r, w r, w r, w r, w r, w r, w r, w r, w sr3h sr3m sr3l dcl vspen x iselh isell r, w r, w r, w r, w r, w r, w r, w r, w sr4h sr4m sr4l en vtop vbot
12 fn6412.1 april 10, 2007 table 7. status register sr1 configuration sr1h sr1m sr1l otf cabf ouvf olf bcf function 0 0 0 x x x x x sr1 is selected 000xxx0xi out
13 fn6412.1 april 10, 2007 received data ( i 2 c bus read mode) the isl6423b can provide to the master a copy of the system register information via the i 2 c bus in read mode. the read mode is master activated by sending the chip address with r/w bit set to 1. at the following master generated clock bits, the isl6423b issues a byte on the sda data bus line (msb transmitted first). at the ninth clock bit the mcu master can: ? acknowledge the reception, starting in this way the transmission of another byte from the isl6423b. ? not acknowledge, stopping the read mode communication. the read only bits of the register sr1 convey diagnostic information about the isl6423b, as indicated in the table 7. power?on i 2 c interface reset the i 2 c interface built into the is l6423b is automatically reset at power-on. the i 2 c interface block will receive a power ok logic signal from the uvlo circuit. this signal will go high when chip power is ok. as long as this signal is low, the interface will not respond to any i 2 c commands and the system register sr1 thru sr4 are all initialized to all zero, thus keeping the power blocks disabled. once the v cc rises above uvlo, the power ok signal to the i 2 c is asserted high, and the i 2 c interface becomes o perative and the sr?s can be configured by the main microprocessor. about 400mv of hysteresis is provided in t he uvlo threshold to avoid false triggering of the powe r-on reset circuit. (i 2 c comes up with en = 0; en goes high at the same time as (or later than) all other i 2 c data for that pwm becomes valid). addr0 and addr1 pins connecting these pin to gnd the chip i 2 c interface address is 0001000, but, it is possible to choose between four different addresses by setting these pins to the logic levels indicated in table 11. table 10. control register sr4 configuration sr4h sr4m sr4l en x x vtop vbot function 0111xx00sr4 is selected 0 1 1 1 x x 0 0 vspen = selvtop = 0, v out = 13v, v boost = 13v + v drop 0 1 1 1 x x 0 1 vspen = selvtop = 0, v out = 14v, v boost = 14v + v drop 0 1 1 1 x x 1 0 vspen = selvtop = 0, v out = 13v, v boost = 13v + v drop 0 1 1 1 x x 1 1 vspen = selvtop = 0, v out = 14v, v boost = 14v + v drop 0 1 1 1 x x 0 0 vspen = 0,selvtop = 1, v out = 18v, v boost = 18v + v drop 0 1 1 1 x x 0 1 vspen = 0,selvtop = 1, v out = 18v, v boost = 18v + v drop 0 1 1 1 x x 1 0 vspen = 0,selvtop = 1, v out = 19v, v boost = 19v + v drop 0 1 1 1 x x 1 1 vspen = 0,selvtop = 1, v out = 19v, v boost = 19v + v drop 0 1 1 1 x x 0 0 vspen = 1,selvtop = x v out = 13v, v boost = 13v + v drop 0 1 1 1 x x 0 1 vspen = 1,selvtop = x v out = 14v, v boost = 14v + v drop 0 1 1 1 x x 1 0 vspen = 1,selvtop = x v out = 18v, v boost = 18v + v drop 0 1 1 1 x x 1 1 vspen = 1,selvtop = x v out = 19v, v boost = 19v + v drop 0 1 1 0 x x x x pwm and linear for channel 1 disabled note: x indicates ?read only? and is a ?don?t care? for the write mode. table 11. address pin characteristics v addr addr1 addr0 v addr -1 ?0001000? 0 0 v addr -2 ?0001001? 0 1 v addr -3 ?0001010? 1 0 v addr -4 ?0001011? 1 1
14 fn6412.1 april 10, 2007 i 2 c bit description i 2 c electrical characteristics bit name description en enable output for channels 1 and 2 vtop voltage top select i.e. 18v, 19v for channels 1 and 2 vbot voltage bottom select i.e. 13v, 14v for channels 1 and 2 ent enable tone msel modulation select dcl dynamic current limit select vspen voltage select pin enable iselh and isell current limit ?i? select high and low bit otf over temperature fault bit cabf cable fault or open status bit ouvf over and under voltage fault status bit olf over load fault status bit bcf backward current fault bit tth tone threshold is the or of the signal pin txt table 12. parameter test condition min typ max input logic high, vih sda, scl 2.0v input logic low, vil sda, scl 0.8v input logic current, iil sda, scl; 0.4v < v dd < 3.3v 10
15 fn6412.1 april 10, 2007 package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6412.1 april 10, 2007 thin shrink small outline expo sed pad plastic packages (eptssop)

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